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agilent HDMP-1685A 1.25 gbps four channel serdes with 5-pin ddr sstl_2 parallel interface data sheet functional description this data sheet describes hdmp- 1685a, a 1.25 gbps, four-channel, 5-pin per channel parallel interface serdes device. the HDMP-1685A 5-pin parallel interface device en- ables a single asic to drive twice as many channels using half as many parallel lines. this is accomplished without increasing the clock frequency by utilizing the bandwidth on the parallel interface more efficiently. the HDMP-1685A serdes is a single silicon bipolar integrated circuit packaged in a 208-pin bga. this integrated circuit provides a low-cost, small-form-factor physical- layer solution for multi-link 1.25 gbps cables or optical trans- ceivers. each ic contains transmit and receive channel circuitry for all four channels. a 125 mhz lvttl reference clock must be supplied to the reference clock input pin, rfct. the transmitter section accepts four, 5-bit-wide parallel sstl_2 data (tx [0:3] [0:4]), a 125 mhz sstl_2 byte clock (tc) and seri- alizes them into four high-speed serial streams. the parallel data is expected to be 8b/10b en- coded data, or equivalent. tx and tc are source synchronous. new data are accepted on both edges of tc; this is called double data rate (ddr). HDMP-1685A finds a sampling window in between the two edges of tc to latch tx [0:3] [0:4] data into the input register of the transmitter section. this timing scheme assumes that the driving asic and HDMP-1685A operate in the same clock domain. 8b/10b encoded data comes in 10-bit characters. this data is latched onto the 5 tx pins of each channel in 5-bit groups. it is ex- pected that the beginning half of each 10-bit character is latched on the rising edge of tc. the transmitter sections pll locks to the 125 mhz tc. this clock is then multiplied by 10 to generate the 1250 mhz serial clock for the high-speed serial outputs. the high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. features ? 5-bit wide tx, rx bus pairs ? 208-ball, 23 mm tbga package ? parallel data i/o and clocks compatible with sstl_2 (eia/jesd8-9) ? 125 mhz tc, rc clocks ? one tc clock for 4 channels ? single or paired rc clocks ? lvttl refclk input ? source synchronous clocking of transmit data ? source centered clocking of receive data ? double data rate (ddr) parallel transfers ? parallel loopback ? differential bll serial i/o ? single +3.3 v power supply ? copper drive capability applications ? high density fast ports ? fast serial backplanes ? clusters of computers ? clusters of network units ? link aggregation, trunks
2 the receiver section accepts four serial electrical data streams at 1250 mbd and recovers the re- spective original 10-bit-wide data for each channel over a 5-pin parallel interface. the receiver pll locks onto the incoming serial signal and recovers the high-speed serial clock and data. the serial data is converted back into 10-bit parallel data, option- ally recognizing the 8b/10b comma character to establish byte alignment. if comma charac- ter detection is enabled by raising the sync signal high, the re- ceiver section is able to detect comma characters and indicate their presence on each channel with the appropriate syn [0:3] signal(s). the recovered parallel data are presented at sstl_2-compatible outputs rx [0:3] [0:4], and a pair of 125 mhz sstl_2 clocks, rc [0:3] [1], and rc [0:3] [0], that are 180 degrees out of phase from one another and which rep- resent the remote clock for that channel. rising edges of rc [0:3] [1] and rc [0:3] [0] may be used to latch rx data at the destination. alternatively, both edges of either rc [0:3] [1] or rc [0:3] [0] may be used to latch rx data (ddr). when sync is high, the beginning half of the comma character shows up at the rising edge of rc [0:3] [1]. the timing of transmit and re- ceive parallel data with respect to tc and rc [0:3] [0:1] is arranged so that the upstream protocol device can generate and latch data very simply. specifically, in the tx direction, the asic drives four sets of 5-pin tx lines and the tc line with the same timing. the tc line is similar to a 6th data line that is always toggling to provide timing information to the serdes. on the rx side, the serdes drives four sets of 5-pin rx data centered between the edges of rc [0:3] [1] or rc [0:3] [0]. for test purposes, the transceiver provides for on-chip parallel loopback functionality controlled through an input pin. addition- ally, the byte-edge alignment feature via detection of the posi- tive comma (k28.5+) character may be disabled. this may be useful in proprietary applications that use alternative methods to align the parallel data. HDMP-1685A block diagram the HDMP-1685A (figure 2) is designed to transmit and receive 10-bit 8b/10b character data over 5-pin-wide parallel busses via high-speed serial communica- tion lines. the parallel data applied to the transmitter is expected to be encoded per the 8b/10b encoding scheme with special reserve characters for link management purposes. other encoding schemes will also work as long as they provide dc bal- ance and sufficient number of transitions. in order to accom- plish this task, the HDMP-1685A incorporates the following: ? sstl_2 parallel data i/o ? high-speed phase locked loops ? parallel-to-serial converters ? high-speed serial clock and data recovery circuitry ? comma character recognition circuitry (k28.5+) ? byte alignment circuitry ? serial-to-parallel converter parallel input latch for each channel, the transmitter accepts 10-bit characters as two groups of 5-pin single-ended sstl_2 parallel data at inputs tx [0:3][0:4]. the sstl_2 tc clock provided by the sender of transmit data is used for all chan- nels as the transmit byte clock. the tx [0:3][0:4] and tc signals must be properly aligned, as shown in figure 3. tx pll/clock generator the transmitter phase locked loop and clock generator (tx pll/clock generator) block generates all internal clocks needed by the transmitter section to perform its functions. these clocks are based on the transmit byte clock (tc). tc is also used to determine the sampling win- dow for the incoming data latches. incoming data is syn- chronous with tc (see figure 3). frame mux the frame mux accepts the 10-bit-wide parallel data from the input latch. using internally generated high-speed clocks, this parallel data is multiplexed into the 1250 mbd serial data streams. the data bits are trans- mitted sequentially, from tx [0] to tx [4]. the leftmost bit of k28.5 is on tx [0]. serial output select the output select block pro- vides a parallel loopback mode for testing purposes. in normal operation, plup is set low and the serialized tx [0:3] [0:4] data are placed at so [0:3] +/-.
3 when parallel wrap-mode is acti- vated by setting plup high, the so [0:3]+/- pins are held static at logic 1 and the serial output signal reflecting tx [0:3] [0:4] data is internally wrapped to the input select block of the re- ceiver section. serial input select the input select block deter- mines whether the signal at si [0:3]+/- or the internal loop- back serial signal is used to drive rx [0:3] [0:4]. in normal opera- tion, plup is set low and the serial data is accepted at si [0:3]+/-. when plup is set high, the out- going high-speed serial signal is internally looped back from the transmitter section to the receiver section. this feature allows par- allel loopback testing, exclusive of the transmission medium. rx pll/clock recovery the rx pll/clock recovery block is responsible for frequency and phase locking onto the in- coming serial data stream and recovering the bit and byte clocks. it does this by continually frequency locking onto the 125 mhz reference clock, and then phase locking onto the se- lected input data stream. an internal signal detection circuit monitors the presence of the input, and invokes the phase detection once the minimum differential input signal level is supplied (ac electrical specifications). once bit locked, the receiver generates the high-speed sam- pling clock at 1250 mhz for the input sampler. serial input sampler the input sampler converts the serial input signal into a retimed bit stream. in order to accomplish this, it uses the high- speed serial clock recovered from the rx pll/clock recovery block. this serial bit stream is sent to the frame demux and byte sync block. frame demux, byte sync the frame demux and byte sync block is responsible for restoring the 10-bit character from the high-speed serial bit stream. this block is also respon- sible for recognizing the comma character (k28.5+) of positive disparity (0011111xxx). when recognized, the frame demux and byte sync block works with the rx pll/clock recov- ery block to properly select the parallel data edge out of the bit stream so that the comma charac- ter starts at rx[0:3][0]. when a comma character is detected and realignment of the receiver byte clock rc[0:3][0:1] is necessary, this clock is stretched, not sliv- ered, to the next possible correct alignment position. this clock will be fully aligned by the start of the second 2-byte or 4-byte ordered set. the second comma character received will be aligned with the rising edge of rc[0:3][1]. comma characters of positive disparity must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. parallel output drivers the output drivers present the recovered 10-bit character in two groups onto the 5-pin rx bus, properly aligned to the re- ceive byte clock rc [0:3] [0:1] as shown in figure 5. these output data buffers provide single-ended sstl_2 compatible signals. un- like the tx, where all four chan- nels are driven with the same transmit byte clock (tc), each receive channel provides its own clock aligned with its own data, so the recovered clocks may not be phase aligned. sstl_2 compatibility HDMP-1685A works with proto- col devices whose vddq voltage is nominally set at 2.5 volts. rx [0:3][0:4], rc [0:3][0:1] pins generate output voltages that are compatible with the sstl_2 standard (eia/jesd8-9). in addi- tion, these devices provide a vrefr output pin allowing the receiving device to differentially detect a high or a low. the devices receive inputs on their tx [0:3][0:4] and tc pins that are also sstl_2 compatible. the vreft input pin is driven by a voltage divider whose supply voltage is at the same level as the vddq supply of the protocol device. this allows differential detection of a high or a low at tx parallel inputs.
4 figure 1. typical application of the four channel serdes. figure 2. block diagram of HDMP-1685A. so0 si0 so1 si1 si2 so2 si3 so3 4-channel asic rc01/0 rx0 tx0 rfct rc11/0 rx1 tx1 rc21/0 rx2 tx2 rc31/0 rx3 tx3 HDMP-1685A tc so[0:3] tx pll clock generator cap0 sl[0:3] rfct rc(0:3)[0:1] syn(0:3) output driver input latch rx(0:3)[0:4] tx(0:3)[0:4] output select frame mux rx pll clock recovery input select frame demux and byte sync input sampler sync cap1 rx clocks tx clocks plup tc
5 HDMP-1685A timing characteristics C transmitter sections t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t txct [2] tx [0:3][0:4] input data and tc clock transition range ps 1600 t txcv [2] tx [0:3][0:4] input data and tc clock valid time ps 2400 t_txlat [1] transmitter latency ns 4 bits 5 note: 1. the transmitter latency, as shown in figure 4, is defined as the time between the leading edge of the first half of a parallel 10-bit word and the leading edge of the first transmitted serial output bit of that 10-bit word. 2. agilents HDMP-1685A internally generates another clock which is 90 degrees out of phase with the tc clock supplied. this clock, which will have its edges at the center of the data valid eye, is used to clock in the tx[0:4] data. setup and hold times are taken care of by the HDMP-1685A provided the specifications indicated are met. figure 3. transmitter section parallel input timing. figure 4. transmitter section latency. tx[0] is first on serial wire. tx [0:3] [0:4] 8 ns txcv tc txcv txct char b[4:0] tx [0:3] [0:4] 10-bit char a so [0:3] 10-bit char b txlat char b[9:5] tc tx[0] tx[9]
6 figure 5a. receiver section parallel output timing using rising edge of both rc[0:3][0] and rc[0:3][1]. HDMP-1685A timing characteristics C receiver sections C rising edge clocking t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f_lock frequency lock at powerup m s 500 b_sync [1,2] bit sync time bits 2500 t rxs rx [0:3][0:4] setup time (data valid before clock) ps 1200 t rxh rx [0:3][0:4] hold time (data valid after clock) ps 800 rc [0:3][1] to rc [0:3][0] skew ns 3.5 4.5 rc [0:3][1] and rc [0:3][0] duty cycle % 40 60 t_rxlat [3] receiver latency ns 16 bits 20 notes: 1. this is the recovery time for input phase jumps, per the fibre channel specification x3.230-1994 fc-ph standard, sec 5.3. 2. tested using c pll = 0.1 m f. 3. the receiver latency, as shown in figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, rc [0:1]). rx [0:3] [0:4] 8 ns rc [0:3] [0] rc [0:3] [1] rxs rxh rxs rxh
7 HDMP-1685A timing characteristics C receiver sections C rising and falling edge clocking t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f_lock frequency lock at powerup m s 500 b_sync [1,2] bit sync time bits 2500 t rxs rx [0:3][0:4] setup time (data valid before clock) ps 1000 t rxh rx [0:3][0:4] hold time (data valid after clock) ps 800 rc [0:3][1] and rc [0:3][0] duty cycle % 40 60 t_rxlat [3] receiver latency ns 16 bits 20 notes: 1. this is the recovery time for input phase jumps, per the fibre channel specification x3.230-1994 fc-ph standard, sec 5.3. 2. tested using c pll = 0.1 m f. 3. the receiver latency, as shown in figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, rc [0:1]). figure 5b. receiver section parallel output timing using rising and falling edge of either rc[0:3][0] or rc[0:3][1]. rx [0:3] [0:4] 8 ns rc [0:3] [0] or rc [0:3] [1] rxs rxh rxs rxh figure 6. receiver section latency. first bit on serial wire drives rx[0:3][0]. char a[4:0] rx [0:3] [0:4] 10-bit char b si [0:3] 10-bit char c rxlat char a[9:5] rc [0:3] [1] rx[0] rx[9] char b[4:0] rc [0:3] [0]
8 HDMP-1685A absolute maximum ratings t a = 25 c, except as specified. sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. symbol parameter units min. max. v cc supply voltage v C0.5 5.0 v in,lvttl rfct lvttl input voltage v C0.7 v cc + 2.8 v in,sstl sstl input voltage v C0.7 v cc + 0.7 v in,hs_in hs_in input voltage (differential) v 2.2 t stg storage temperature c C65 +150 t j junction temperature c 0 +125 t c case temperature c0 95 HDMP-1685A guaranteed operating rates t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v parallel clock rate (mhz) serial baud rate (mbaud) min. max. min. max. 124.0 126.0 1240 1260 HDMP-1685A reference clock and transmit byte clock requirements t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f nominal frequency mhz 125 f tol frequency tolerance ppm C100 +100 symm rfc symmetry (duty cycle) reference clock % 40 60 symm tc symmetry (duty cycle) transmit byte clock % 40 60 HDMP-1685A lvttl i/o dc electrical specifications t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. v ih,lvttl lvttl input high voltage level, v 2 5.5 guaranteed high signal for all inputs v il,lvttl lvttl input low voltage level, v 0 0.8 guaranteed low signal for all inputs v oh,lvttl lvttl output high voltage level, i oh = C400 m a v 2.2 v cc v ol,lvttl lvttl output low voltage level, i ol = 1 ma v 0 0.5 i ih,lvttl input high current, v in = 2.4 v, v cc = 3.45 v m a40 i il,lvttl input low current, v in = 0.4 v, v cc = 3.45 v m a C600
9 HDMP-1685A sstl_2 i/o dc electrical parameters t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v, vddq = 2.30 v to 2.70 v. vddq is the fc-1/mac device i/o supply voltage. sstl-2 inputs can receive lvttl signals successfully. sstl-2 outputs do not output lvttl compliant levels. symbol parameter units min. typ. max. vreft sstl_2 input reference voltage v 1.15 1.25 1.35 v ih input high voltage v vreft +0.18 vddq +0.30 v il input low voltage v C0.30 vreft C0.18 vrefr sstl_2 output reference voltage v 1.15 1.25 1.35 v oh output high voltage v vrefr +0.38 vddq v ol output low voltage v gnd vrefr C0.38 HDMP-1685A ac electrical specifications (trx) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. t r,rfct rfct lvttl input rise time, 0.8 to 2.0 volts ns 0 2.4 t f,rfct rfct lvttl input fall time, 2.0 to 0.8 volts ns 0 2.4 t r,sstlo sstl output rise time, 1.0 v to 1.6 v ns 0.4 1.5 t f,sstlo sstl output fall time, 1.6 v to 1.0 v ns 0.28 1.5 t rs, hs_out hs_out single-ended (so[0:3] ) rise time (20% - 80%) ps 85 205 300 t fs, hs_out hs_out single-ended (so[0:3] ) fall time (20% - 80%) ps 85 180 300 t rd, hs_out hs_out differential rise time ps 85 300 t fd, hs_out hs_out differential fall time ps 85 300 v ip,hs_in hs_in (si[0:3] ) input peak-to-peak differential voltage mv 200 1200 2000 v op,hs_out [1] hs_out output pk-pk diff. voltage (z0=50 ohms, fig.10) mv 1000 1300 1800 figure 7. eye diagram of a high speed differential output. note: 1. output peak-to-peak differential voltage specified as so[0:3]+ minus so[0:3]C. the amplitude will be 25% higher when terminating into 75 w loads. 130.3664 ns 120.0 ps/div x1 x2 yx 1 (f2) = ?37.00 mv 2 (f2) = 636.00 mv 130.549 ns 131.349 ns 800 ps 1.250 ghz waveform math f1 = 3 ?4 f2 = 1 ?2 function f2 f1 define function... display on off vertical scale manual auto y scale y offset 250 mv/div 0.0 v d = 1.27300 v 1/ d x =
10 note: 1. defined by fibre channel specification x3.230-1994 fc-ph standard, annex a, section a.4 and tested using measurement method shown in figure 8. figure 8. transmitter jitter measurement method. HDMP-1685A output jitter characteristics C transmitter section t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. rj [1] random jitter at dout, the high speed electrical data port, ps 11 specified as 1 sigma deviation of the 50% crossing point (rms) dj [1] deterministic jitter at dout, the high speed electrical data port (pk-pk) ps 26 note: 1. based on independent package testing by agilent. q ja for these devices is 36 c/w for the HDMP-1685A. q ja is measured on a standard 3x3" fr4 pcb in a still air environment. to determine the actual junction temperature in a given application, use the following: tj = tc + ( q jc x p d ), where tc is the case temperature measured on the top center of the package and p d is the power being dissipated. HDMP-1685A thermal and power temperature characteristics (trx) t a = 0 c to t c = 85 c, v cc = 3.15 v to 3.45 v symbol parameter units typ. max. i cc,trx transceiver v cc supply current, t a = 25 c ma 900 p d, trx [1] transceiver power dissipation, outputs connected w 2.97 3.5 per recommended bias terminations with 2 7 C1 prbs pattern q jc [1] thermal resistance, junction to case c/w 7.8 t j junction temperature (absolute maximum) c 0 +125 t c case temperature (absolute maximum) c 0 +95 a 70841b pattern generator a 83480a oscilloscope hdmp-1685 a 70311a clock source + data - data +k28.5, -k28.5 trigger ch1 ch2 soi+ soi tc plup txi[0:4] 1.25 ghz 125 mhz sync rxi[0:4] sii sii+ divide by 2 divide by 10 circuit variable delay b. block diagram of dj measurement method HDMP-1685A a 70841 pattern generator a 83480a oscilloscope hdmp-1685 a 70311a clock source + data - data 1000001111 trigger ch1 ch2 soi+ soi tc plup txi[0:4] 0011111000 (static k28.7) 125 mhz a. block diagram of rj measurement method bias tee 1.4 v
11 figure 9. lvttl input simplified circuit schematic (for rfct). figure 10. hs_out and hs_in simplified circuit schematic. v bb 1.4 v gnd v cc i_ttl gnd esd protection v cc v cc hs_out zo = 50 w zo = 50 w v ccp gnd esd protection so[0:3] so[0:3]+ gnd si[0:3]+ si[0:3] esd protection + + hs_in 2 * zo = 100 w v cc gnd gnd v cc notes: 1. hs_in inputs should never be connected to ground as permanent damage to the device may result. 2. capacitors may be placed at the sending end or the receiving end. zo zo 0.01 ? 0.01 ? HDMP-1685A i/o type definitions i/o type definition i-lvttl input lvttl, floats high when left open i-sstl2 input sstl_2, floats low when left open o-sstl2 output sstl_2 hs_out 50 w matched output driver. will drive ac coupled 50 w loads. pecl level compatible (figure 10). hs_in pecl level compatible. must be ac coupled (figure 10). c external circuit node s power supply or ground HDMP-1685A pin input capacitance (trx) symbol parameter units typ. max. c input input capacitance on sstl input pins pf 1.6
12 figure 12. pinout of HDMP-1685A (top view). figure 11. o-sstl_2 and i-sstl_2 simplified circuit schematic. 01 gnd rx04 rx00 rc00 tx14 tx10 tx04 tx00 vrft rfct gnd u t r p n m l k j h g a b c d e f 02 v cc rx01 rc01 tx11 tx01 gnd syn0 gnd 03 gnd vcr0 rx02 tx12 tx02 sioe vcr0 v cc gnd gnd gnd gnd 04 syn1 gnd rx03 tx13 tx03 si0+ gnd v cc v cc gnd v cc v cc gnd vcr0 gnd 05 rc10 gnd v cc vcp0 so0+ rc11 vcr1 so0e 06 rx10 rx13 si1e gnd gnd rx11 rx12 gnd 07 rx14 vrfr si1+ vcp1 so1+ vcr1 gnd so1e 08 gnd gnd gnda gnd 09 gnd v cca cap1 cap0 vcr1 gnd 10 si2e gnd gnd gnd v cc syn2 rc20 rc21 11 si2+ vcp2 so2e so2+ gnd rx20 vcr2 gnd 12 gnd gnd gnd gnd rx21 rx22 rx23 rx24 13 si3e vcp3 so3e so3+ vcr2 14 rx31 vcr3 v cc plup si3+ v cc tx22 gnd tx33 v cc v cc 15 rx32 gnd v cc gnd gnd tx21 gnd tx32 gnd vcr3 gnd syn3 16 rx33 gnd gnd tx20 v cc tx31 v cc gnd vcr2 rc30 tx24 17 rx34 gnd vcr3 tc tx30 sync rx30 gnd rc31 tx23 gnd tx34 gnd v cc gnda v ccp v cca vcr vrefr v cc rx[0:3][0:4] rc[0:3][0:1] tx[0:3][0:4] tc vreft hdmp-1685 r 1 r 2 v ddq (mac) vreft v cc datain dataout mac v cc (serdes) = 3.3 v v cc (mac) vddq v ddq (mac) rs = 50 w use termination, if necessary, to deliver proper voltage swings at tx[0:4] rs = 50 w unterminated 0.1 ? r 1 r 2 v cc (serdes) = 3.3 v 0.1 ? note: vrefr on each device may be used to drive vreft on the other device instead of using the configuration above. vrefr should be bypassed with 0.1 ? in this case. if used, r 1 and r 2 should be 500-1000 w . 1% resistors should be used for r 1 and r 2 . when using the configuration above, vreft to the mac should be set to 1.25 v nominal. using this value centers vrefr relative to the rx[0:3][0:4] output swings provided by the HDMP-1685A.
13 filtering schematic gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcr vcr vcr vcr vcr vcr vcr vcr vcr vcr vcr vcr v cc a v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc vcp vcp vcp vcp 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 10 m f* 10 m f 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 a b c d e f g h j k l m n p r t u * 10 f placement not critical ?indicates need for low-frequency bypass capacitance HDMP-1685A to v cc a pi-filter (see schematic) vcr v cc HDMP-1685A guidelines for decoupling capacitor placements/connections r4 v cc vcr vcr vcr v cc v cc v cc v cc vcr vcr vcr vcr v cc v cc v cc vcr vcr v cc vcr vcr v cc v cc vcp v cc vcp v cca vcp vcp v cc v cc r14 a2 0.1 ? 0.1 ? + + 1 ? 0.1 ? l4 g4 0.1 ? c4 c5 d3 f3 0.1 ? b7 a9 a10 a13 a16 10 ? 0.1 ? c11 c14 c15 e14 g17 k16 n15 j14 r16 t14 t13 t11 + 10 ? t7 t3 u5 t5 t4 t9 0.1 ? 0.1 ? 0.1 ? 0.1 ? 0.1 ? 0.1 ? 0.1 ? v cc 10 ? 0.1 ? v cc * + * + placement not critical. indicates the need for additional low frequency capacitive decoupling. optional ?provides increased low frequency decoupling.
14 HDMP-1685A trx i/o definition name pin type signal cap0 p09 c loop filter capacitor: a loop filter capacitor for the internal plls must be connected across the cap0 and cap1 pins. (typical value = 0.1 m f) cap1 r09 plup n14 i-sstl2 parallel loopback enable input: when set high, a high-speed serial signal from the transmitter sections serial output select block, reflecting tx data, is driven to the receiver sections serial input select block. rx data reflects this serial signal. also when in parallel loopback mode, the so [0:3]+/- outputs are held static at logic 1. rfct r01 i-lvttl lvttl reference clock: rfct is a 125 mhz clock signal supplied to the ic. rc00 e01 o-sstl2 receiver byte clocks: the receiver sections drive 125 mhz receive byte rc01 e02 clocks rc [0:3] [0:1]. rc10 a05 rc11 b05 rc20 c10 rc21 d10 rc30 b16 rc31 b17 rx00 d01 o-sstl2 data outputs: four 5-pin data busses. rx [0:3] [0] are the first bits received. rx01 d02 rx02 e03 rx03 e04 rx04 c01 rx10 a06 rx11 b06 rx12 c06 rx13 d06 rx14 a07 rx20 b11 rx21 a12 rx22 b12 rx23 c12 rx24 d12 rx30 c17 rx31 d14 rx32 d15 rx33 d16 rx34 d17 si0+ u04 hs_in serial data inputs: high-speed inputs. serial data are accepted from the si [0:3]+/- si0- u03 inputs except when plup is high. si1+ u07 si1- u06 si2+ u11 si2- u10 si3+ u14 si3- u13
15 HDMP-1685A trx i/o definition, continued name pin type signal so0+ r05 hs_ out serial data outputs: high-speed outputs. these lines are active except when so0- p05 plup is high, in which case these outputs are held static at logic 1. so1+ r07 so1- p07 so2+ p11 so2- r11 so3+ p13 so3- r13 sync r17 i-sstl2 enable byte sync input: when high, turns on the internal byte sync functions to allow clock synchronization to a comma character of positive disparity (0011111xxx). when the line is low, the function is disabled and will not reset registers and clocks, or strobe the syn [0:3] lines. syn0 f02 o-sstl2 byte sync outputs: active high outputs. used to indicate detection of a comma syn1 a04 character of positive disparity (0011111xxx) when sync is enabled. syn2 b10 syn3 b15 tc k17 i-sstl2 transmit byte clock: this signal is used to latch transmit data for all channels into the ic. tx00 n01 i-sstl2 data inputs: four 5-pin data busses. tx [0:3] [0] are the first bits transmitted. tx01 n02 tx02 n03 tx03 n04 tx04 m01 tx10 j01 tx11 j02 tx12 j03 tx13 j04 tx14 h01 tx20 g16 tx21 g15 tx22 g14 tx23 h17 tx24 h16 tx30 l17 tx31 l16 tx32 l15 tx33 l14 tx34 m17 vreft p01 i-s tx parallel interface sstl_2 reference voltage: voltage reference derived from 2 resistor network with v ddq (asic) as supply, as recommended in figure 11. vrefr d07 o-s rx parallel interface sstl_2 reference voltage: provided by HDMP-1685A. drives the vref input of the asic.
16 HDMP-1685A trx i/o definition, continued name pin type signal v cc a02 s power supply: normally 3.3 volts. used for logic, sstl inputs, and lvttl i/o. a10 c14 g04 j14 k16 l04 n15 r04 r14 r16 t03 t04 t14 u05 vcca t09 s analog power supply: normally 3.3 volts. used to provide a clean supply line for the plls and high-speed analog cells. vcr0 c04 s rx sstl2 output power supply: normally 3.3 volts. used for all sstl2 receiver d03 output buffer cells. f03 vcr1 a09 b07 c05 vcr2 a13 a16 c11 vcr3 c15 e14 g17 vcp0 t05 s high-speed output supply: normally 3.3 volts. used only for the last stage vcp1 t07 of the high-speed transmitter output cells (hs_out) as shown in figure 10. vcp2 t11 due to high current transitions, this v cc should be well bypassed to a ground plane. vcp3 t13 gnda r08 s analog ground: normally 0 volts. all gnd pads on the chip are connected to one ground slug in the package, which then distributes these to gnd balls.
17 HDMP-1685A trx i/o definition, continued name pin type signal gnd a01 s logic ground: normally 0 volts. all gnd pads on the chip are connected to one a03 ground slug in the package, which then distributes these to gnd balls. a11 a15 a17 b04 b09 c07 c16 d04 d05 d11 e15 f04 f17 g03 k03 k04 k14 k15 l03 p04 p06 p08 p10 p12 r03 r06 r10 r12 r15 t02 t06 t08 t10 t12 t15 t16 u01 u02 u08 u09 u12 u15 u16 u17
18 HDMP-1685A trx i/o definition, continued name pin type signal nc a08 these pins are connected to an isolated pad and have no functionality. a14 they may be left open, or lvttl levels may be applied. b01 b02 b03 b08 b13 b14 c02 c03 c08 c09 c13 d08 d09 d13 e16 e17 f01 f14 f15 f16 g01 g02 h02 h03 h04 h14 h15 j15 j16 j17 k01 k02 l01 l02 m02 m03 m04 m14 m15 m16 n16 n17 p02 p03 p14 p15 p16 p17 r02 t01 t17
19 package drawing z ddd detail a [?? seating plane a a2 d e [?? [?? seating plane a1 a3 (backfill) [?? detail a e1 nx0b e s d1 e s o (4x) y ? eee a b c d e 12345 (cavity down) (backfill) x z m a1 corner symbol min. nom. max. a 1.35 1.50 1.65 a1 0.60 0.65 0.70 a2 0.85 0.90 0.95 a3 0.15 d 23.00 ?0.20 d1 20.32 bsc e 23.00 ?0.20 e1 20.32 bsc md/me 17 n 208 n1 4 o 0.60 b 0.60 0.75 0.90 e 1.27 ?0.10 dimensions in millimeters symbol min. nom. max. ddd 0.15 eee 0.30 tolerance of form and position
www.semiconductor.agilent.com data subject to change. copyright ? 2001 agilent technologies, inc. may 7, 2001 obsoletes 5988-1304en 5988-2143en

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